VLSI Architectures for modern error correcting codes

 VLSI Architectures for modern error correcting codes

VLSI Architectures for modern error correcting codes

Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability.

On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges.

It is difficult to follow the vast amount of literature to develop efficient very large scale integrated (VLSI) implementations of en/decoders for stateof-the-art error-correcting codes.

The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements.

This book can also be used as a reference for graduate courses on VLSI design and error-correcting coding.

Particularly, the emphases are given to soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, binary and non-binary low-density parity-check (LDPC) codes.

These codes are among the best candidates for modern and emerging applications, due to their good error-correcting performance and lower implementation complexity compared to other codes.

To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.

Although many books have been published on both coding theory and circuit design, no book explains the VLSI architecture design of state-of-the-art error-correcting codes in great detail.

High-performance error-correcting codes usually involve complex mathematical computations. Mapping them directly to hardware often leads to very high complexity.

This book serves as a bridge connecting advancements in coding theory to practical hardware implementations.

Instead of circuit-level design techniques, focus is given to integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation.

The first part of this book (Chapters 1 and 2) introduces some fundamentals needed for the design and implementation of error-correcting codes.

Specifically, Chapter 1 focuses on the implementation of finite field arithmetic, which is the building block of many error-correcting coding and cryptographic schemes.

Chapter 2 briefly introduces commonly-used techniques for achieving speed, area, and/or power consumption tradeoffs in hardware designs.

The second part (Chapters 3-7) of this book is devoted to the implementation of RS and BCH codes. Simplification techniques and VLSI architectures are presented in Chapter 3 for root computation of polynomials over finite fields, which is a major functional block in both hard- and soft-decision RS and BCH decoders.

Chapter 4 gives the encoding and hard-decision decoding algorithms of RS codes and their implementation architectures.

Transformations for lowering the complexity of algebraic soft-decision (ASD) RS decoding algorithms and their implementations are discussed thoroughly in Chapter 5.

Chapter 6 focuses on the interpolation-based Chase decoder, which is one special case of ASD decoders, and it achieves a good performance-complexity tradeoff. BCH encoder and decoders, including both hard-decision and soft-decision Chase decoders, are presented in Chapter 7.

The third part of the book (Chapters 8 and 9) addresses the implementation of LDPC decoders. Decoding algorithms and VLSI architectures for binary and non-binary LDPC codes are presented, compared, and discussed in Chapters 8 and 9, respectively.

Chapter 1 of this book reviews finite field arithmetic and its implementation architectures. Besides error-correcting codes, such as RS, BCH, and LDPC codes, cryptographic schemes, including the Advanced Encryption Standard (AES) and elliptic curve cryptography, are also defined over finite fields.

Definitions and properties of finite fields are first introduced. Then the implementation architectures of finite field operations using different representations of field elements, such as standard basis, normal basis, dual basis, composite field, and power presentation, are detailed and compared.

The conversions among different representations are also explained. To assist the understanding of the en/decoder designs presented in later chapters, some fundamental concepts used in VLSI architecture design are introduced in Chapter 2. Brief discussions are given to pipelining, retiming, parallel processing, and folding, which are techniques that can be used to manipulate circuits to trade off speed, silicon area, and power consumption.


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